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Functional Description
GENERAL DESCRIPTION
LMX2522/32 is a highly integrated frequency synthesizer
system that generates LO signals for PCS, Cellular CDMA
and GPS systems. These devices include all of the func-
tional blocks of a PLL, RF VCO, prescaler, RF phase detec-
tor, and loop filter. The need for external components is
limited to a few passive elements for matching the output
impedance and bypass elements for power line stabilization.
In addition to the RF circuitry, the IC also includes IF fre-
quency dividers, and an IF phase detector to complete the IF
synthesis with an external VCO and loop filter. Table 4
summarizes the counter values to generate the default IF
frequencies.
Using a low spurious fractional-N synthesizer based on a
delta sigma modulator, the circuit can support 10 kHz chan-
nel spacing for PCS, Cellular CDMA and GPS systems.
The fractional-N synthesizer enables faster lock time, which
reduces power consumption and system set-up time. Addi-
tionally, the loop filter occupies a smaller area as opposed to
the integer-N architecture. This allows the loop filter to be
embedded into the circuit, minimizing the external noise
coupling and total form factor. The delta sigma architecture
delivers very low spurious, which can be a significant prob-
lem for other PLL solutions.
The circuit also supports commonly used reference frequen-
cies of 19.20 MHz and 19.68 MHz.
FREQUENCY GENERATION
RF-PLL Section
The divide ratio can be calculated using the following equa-
tion:
LMX2522 – PCS CDMA:
f
VCO = {8 x RF_B + RF_A + (RF_FN / fOSC)x10
4}xf
OSC
where (RF_A < RF_B)
LMX2532 – Cellular CDMA:
f
VCO = {6 x RF_B + RF_A + (RF_FN / fOSC)x10
4}xf
OSC
where (RF_A < RF_B)
where
f
VCO: Output frequency of voltage controlled oscillator (VCO)
RF_B: Preset divide ratio of binary 4-bit programmable
counter (2
≤ RF_B ≤ 15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0
≤
RF_A
≤ 7 for LMX2522 or 0 ≤ RF_A ≤ 5 for LMX2532)
RF_FN: Preset numerator of binary 11-bit modulus counter
(0
≤ RF_FN < 1920 for f
OSC = 19.20 MHz or 0
≤ RF_FN <
1968 for f
OSC = 19.68 MHz)
f
OSC: Reference oscillator frequency
GPS-PLL SECTION
The divide ratio can be calculated using the following equa-
tion:
LMX2522 – PCS CDMA:
f
VCO = {6 x RF_B + RF_A + (RF_FN / fOSC)x10
4}xf
OSC
where (RF_A < RF_B)
LMX2532 – Cellular CDMA:
f
VCO = {8 x RF_B + RF_A + (RF_FN / fOSC)x10
4}xf
OSC
where (RF_A < RF_B)
where
f
VCO: Output frequency of voltage controlled oscillator (VCO)
RF_B: Preset divide ratio of binary 4-bit programmable
counter (2
≤ RF_B ≤ 15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0
≤
RF_A
≤ 5 for LMX2522 or 0 ≤ RF_A ≤ 7 for LMX2532)
RF_FN: Preset numerator of binary 11-bit modulus counter
(0
≤ RF_FN < 1920 for f
OSC = 19.20 MHz or 0
≤ RF_FN <
1968 for f
OSC = 19.68 MHz)
f
OSC: Reference oscillator frequency
PCS CDMA applications using the LMX2522, if the GPS
frequency is 1355.04 MHz, Table 1 provides the proper
register settings:
TABLE 1. Settings for GPS (1355.04 MHz) in LMX2522
PCS CDMA application
Reference Frequency
RF_B
RF_A
RF_FN
19.20 MHz
11
4
1104
19.68 MHz
11
2
1680
Cellular CDMA applications using the LMX2532, in which the
GPS frequency is 1490.04 MHz, then Table 2 provides the
proper register settings:
TABLE 2. Settings for GPS (1490.04 MHz) in LMX2532
Cellular CDMA application
Reference Frequency
RF_B
RF_A
RF_FN
19.20 MHz
9
5
1164
19.68 MHz
9
3
1404
Cellular CDMA applications using the LMX2532, in which the
GPS frequency is 1391.82 MHz, then Table 3 provides the
proper register settings:
TABLE 3. Settings for GPS (1391.82 MHz) in LMX2532
Cellular CDMA application
Reference Frequency
RF_B
RF_A
RF_FN
19.20 MHz
9
0
942
19.68 MHz
8
6
1422
IF-PLL SECTION
f
VCO = {16 x IF_B + IF_A} x fOSC / IF_R where (IF_A < IF_B)
where
f
VCO: Output frequency of the voltage controlled oscillator
(VCO)
IF_B: Preset divide ratio of the binary 9-bit programmable
counter (1
≤ IF_B ≤ 511)
IF_A: Preset divide ratio of the binary 4-bit swallow counter
(0
≤ IF_A ≤ 15)
f
OSC: Reference oscillator frequency
IF_R: Preset divide ratio of the binary 9-bit programmable
reference counter (2
≤ IF_R ≤ 511)
From the above equation, the LMX2522/32 generates the
fixed IF frequencies as summarized in Table 4.
LMX2522/LMX2532
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